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SPT7750
8-BIT, 500 MSPS, FLASH A/D CONVERTER TECHNICAL DATA
FEATURES
* * * * * * 1:2 Demuxed ECL compatible outputs Wide input bandwidth - 900 MHz Low input capacitance - 15 pF Metastable errors reduced to 1 LSB Monolithic for low cost Gray code output
APPLICATIONS
* * * * Digital oscilloscopes Transient capture Radar, EW, ECM Direct RF down-conversion
NOVEMBER 30, 2001
GENERAL DESCRIPTION
The SPT7750 is a full parallel (flash) analog-to-digital converter capable of digitizing full scale (0 to -2 V) inputs into eight-bit digital words at an update rate of 500 MSPS. The ECL-compatible outputs are demultiplexed into two separate output banks, each with differential data ready outputs to ease the task of data capture. The SPT7750's wide input bandwidth and low capacitance eliminate the need
for external track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The SPT7750 operates from a single -5.2 V supply, with a nominal power dissipation of 5.5 W. The SPT7750 is available in an 80-lead surface-mount MQuad package over the industrial temperature range (-25 C to +85 C) and in die form.
BLOCK DIAGRAM
Analog VRT Input Preamp Comparator 256
CLK CLK CLOCK BUFFER DEMUX CLOCK BUFFER
255
D8 (OVR) D7 (MSB) D6
DRB (DATA READY) D8B D7B D6B D5B D4B D3B D2B DRB (DATA READY) D8B (OVR) D7B (MSB) D5B D6B
152
256 TO 8 Bit Decoder With Metastable Error Correction
ECL Output Buffers And Latches
151
D4B D3B D2B D1B D0B (LSB) DRA (DATA READY) DRA (DATA READY) D8A (OVR) D7A (MSB) D5A D4A D3A D2A D1A D0A (LSB) D6A
1:2 DEMULTIPLEXER
128
D5
D1B D0B
VRM
127
D4
D8A D7A D6A D5A D4A D3A D2A D1A D0A
64
D3
63
D2
2
D1
1
D0 (LSB)
VRB
BANK A
BANK B
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages Negative Supply Voltage (VEE TO GND) -7.0 to +0.5 V Ground Voltage Differential .................... -0.5 to +0.5 V Input Voltage Analog Input Voltage ............................... +0.5 V to VEE Reference Input Voltage .......................... +0.5 V to VEE Digital Input Voltage ................................ +0.5 V to VEE Reference Current VRT to VRB ........................... 35 mA Output Digital Output Current ............................... 0 to -28 mA Temperature Operating Temperature, ambient ............ -25 to +85 C case .......................... +125 C junction ..................... +150 C Lead Temperature, (soldering 10 seconds) ..... +300 C Storage Temperature ............................ -65 to +150 C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TJ = TC = TA = +25 C , VEE=-5.2 V, VRB=-2.0 V, VRM=-1.0 V, VRT=0.00 V, CLK=500 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS Resolution DC Accuracy Integral Linearity Error (ILE) Differential Linearity Error (DLE) No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth Small Signal Large Signal Offset Error VRT Offset Error VRB Input Slew Rate Clock Synchronous Input Currents Reference Input Ladder Resistance Reference Bandwidth Timing Characteristics Maximum Sample Rate Aperture Jitter Acquisition Time CLK to Data Ready Delay Clock to Data Delay Dynamic Performance Signal-To-Noise Ratio (without Harmonics) IN = 50 MHz IN = 250 MHz Total Harmonic Distortion IN = 50 MHz IN = 250 MHz Signal-to-Noise and Distortion IN = 50 MHz IN = 250 MHz
TEST CONDITIONS
TEST LEVEL
MIN
SPT7750A TYP MAX 8
MIN
SPT7750B TYP MAX UNITS 8 Bits +1.5 +1.5 Guaranteed LSB LSB
CLK = 100 kHz CLK = 100 kHz
I I
-1.0 -0.85 Guaranteed
+1.0 +0.95
-1.5 -0.95
VIN=0 V Over Full Input Range
I I V V V V IV IV V V I V I V V IV IV
VRB .75 15 15 900 500 -30 -30 5 2 60 80 30
VRT 2.0
VRB .75 15 15 900 500
VRT 2.0
V mA k pF MHz MHz mV mV V/ns A MHz MHz ps ps ns ns
+30 +30
-30 -30 5 2 60 80 30
+30 +30
500 0.9 1.25 2 250 1.4 1.75 1.9 2.25
500 0.9 1.25 2 250 1.4 1.75 1.9 2.25
I I I I I I
47 44 -46 -38 43 37
45 42 -44 -36 41 35
dB dB dBc dBc dB dB
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ELECTRICAL SPECIFICATIONS
TJ = TC = TA = +25 C , VEE=-5.2 V, VRB=-2.0 V, VRM=-1.0 V, VRT=0.00 V, CLK=500 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS Dynamic Performance Spurious Free Dynamic Range IN = 50 MHz IN = 250 MHz Digital Inputs Input High Voltage (CLK, CLK) Input Low Voltage (CLK, CLK) Clock Pulse Width High (tPWH) Clock Pulse Width Low (tPWL) Digital Outputs Logic 1 Voltage Logic 0 Voltage Rise Time Fall Time Power Supply Requirements Voltage VEE Current IEE Power Dissipation
TEST CONDITIONS
TEST LEVEL
MIN
SPT7750A TYP MAX
MIN
SPT7750B TYP MAX UNITS
I I
49 41
44 36
dB dB
I I I I I I V V IV I I
-1.1 1.0 1.0 -1.1
-0.7 -1.8 0.67 0.67 -0.9 -1.8 450 450 -5.2 1.05 5.5 -1.5
-1.1 1.0 1.0 -1.1 -1.5
-0.7 -1.8 0.67 0.67 -0.9 -1.8 450 450 -5.2 1.05 5.5 -1.5
V V ns ns V V ps ps
-1.5
20% to 80% 20% to 80%
-4.95
-5.45 1.2 6.25
-4.95
-5.45 V 1.2 A 6.25 W
Typical Thermal Impedance: JC = +4 C/W.
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all test are pulsed tests; therefore, TJ = TC = TA.
LEVEL
I II III IV V VI
TEST PROCEDURE
100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
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GENERAL DESCRIPTION
The SPT7750 is one of the fastest monolithic 8-bit parallel flash A/D converters available today. The nominal conversion rate is 500 MSPS and the analog bandwidth is in excess of 900 MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see block diagram). This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta, but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage and frequency ranges and therefore Figure 1 - SPT7750 Typical Interface Circuit
DRB VIN** 50 W VIN VIN DRB DRA
makes the part easier to drive than previous flash converters. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to "trip" into or out of the active state. This gain reduces metastable states that can cause errors at the output. The SPT7750 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50 loads.
U3
DRB (DATA READY) DRB (DATA READY) DRA (DATA READY)
50 W
50 W
DRA
U3
DRA (DATA READY) 2.0 V Pulldown (Digital)
VRTF R 22 W VRTS
D8B (OVR) D7B (MSB) D6B D5B D4B D3B D2B D1B D0B (LSB) D8A (OVR) D7A (MSB) D6A D5A D4A D3A D2A D1A D0A (LSB)
+ U1 R
*
VRM
Convert
U2
CLK CLK 50 W 50 W
AGND DGND
50 W
50 W
VEE
+
2.0 V Reference
22 W 2N2907
U1
VRBS VRBF
*
5.2 V
5.2 V
.1 F FB = Ferrite bead
2.0 V Pulldown (Digital)
2 V Pulldown (Analog)
U1 = OP291 or equivalent with low offset/noise. R = 1 kW; 0.1% matched. = AGND = DGND U2 = ON Semiconductor ECLinPS LITE, MC10EL16, differential receiver with 250 ps (typ) propagation delay. U3 = MC10EL16 or MC100EL16. * = 10 F Tantalum Capacitor and 0.1 F Chip Capacitor
*
5.2 V
FB
** = Care must be taken to avoid exceeding the maximum rating for the input, especially during power up sequencing of the analog input driver.
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TYPICAL INTERFACE CIRCUIT
The circuit in figure 1 is intended to show the most elaborate method of achieving the least error by correcting for integral linearity, input induced distortion, and power supply/ground noise. This is achieved by the use of external reference ladder tap connections, input buffer, and supply decoupling. Please contact the factory for the SPT7750 evaluation board application note that contains more details on interfacing the SPT7750. The function of each pin and external connections to other components is as follows: VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a .01 F ceramic capacitor. A 10 F tantalum can also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 1. VIN (ANALOG INPUT) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The SPT7750 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. CLK, CLK (CLOCK INPUTS) The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. D0 TO D8, DR, DR, (A AND B) The digital outputs can drive 50 to ECL levels when pulled down to -2 V. When pulled down to -5.2 V, the outputs can drive 130 to 1 k loads. All digital outputs are grey code with the coding as shown in table I. Fairchild recommends using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times.
VRBF, VRBS, VRTF, VRTS, VRM (REFERENCE INPUTS) There are two reference inputs and one external reference voltage tap. These are -2 V (VRB force and sense), midtap (VRM) and AGND (VRT force and sense). The reference pins and tap can be driven by op amps as shown in figure 1 or VRM may be bypassed for limited temperature operation. These voltage inputs can be bypassed to AGND for further noise suppression if so desired. Table I - Output Coding
VIN >-0.5 LSB -0.5 LSB -1.5 LSB * * * -1.0 V * * * -2.0 V +0.5 LSB <(-2.0 V +0.5 LSB) D8 1 1 0 0 0 * * * 0 0 * * * 0 0 0 D7 . . . D8 10000000 10000000 10000000 10000000 10000001 * * * 11000000 01000000 * * * 00000001 00000000 00000000
Indicates the transition between the two codes
THERMAL MANAGEMENT The typical thermal impedance is as follows: CA = +17 C/W in still air with no heat sink We highly recommend that a heat sink be used for this device with adequate air flow to ensure rated performance of the device. We have found that a Thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal performance under laboratory tests. Application specific conditions should be taken into account to ensure that the device is properly heat sinked.
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OPERATION
The SPT7750 has 256 preamp/comparator pairs which are each supplied with the voltage from VRT to VRB divided equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each one's individual clock buffer. When the CLK pin is in the low state, the master or input stage of the comparators compare the analog input voltage to the respective reference voltage. When the CLK pin changes from low to high the comparators are latched to the state Figure 2 - Timing Diagram
prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRT (0 V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when the CLK is changed from high to low. At the output of the decoders is a set of four 7-bit latches which are enabled ("track") when the clock changes from high to low. From here, the output of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs.
N VIN
N+1 N+2 2.0 ns N+3 N+4
N+5
N+6
CLK CLK DRA DRA Data Bank A N-2
1.4 ns typ 1.75 ns typ 1.75 ns typ
N
N+2
N+4
DRB DRB Data Bank B N-1
1.4 ns typ
N+1
N+3
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Figure 3 - Subcircuit Schematics Input Circuit
AGND
Output Circuit
AGND DGND
Clock Input
AGND
VIN
VR
CLK CLK
Data Out
VEE
VEE
PACKAGE OUTLINE
80-Lead MQuad
F G H I
Symbol A B C D E F G H I J K L M Inches Min Max 0.904 0.923 0.777 0.781 0.472 typ 0.541 0.545 0.667 0.687 0.031 typ 0.012 0.018 0.109 0.134 0.010 0.024 0.724 typ 0.099 0.110 0 7 0.029 0.041 Millimeters Min Max 22.95 23.45 19.74 19.84 12.00 typ 13.74 13.84 16.95 17.45 0.80 typ 0.30 0.45 2.76 3.40 0.25 0.60 18.40 typ 2.51 2.80 0 7 0.73 1.03
AB
J
C D E
K
M L
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PIN ASSIGNMENTS
D1B VEE D0B DGND DRB DGND DRB DGND D8A DGND D7A DGND D6A VEE D5A D4A
PIN FUNCTIONS
NAME VEE AGND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 N/C N/C D3A D2A VEE D1A DGND D0A DGND DRA DGND DRA AGND AGND CLK VEE CLK VEE VEE AGND AGND VRTS VRTF N/C
FUNCTION Negative Supply Nominally -5.2 V Analog Ground Reference Voltage Force Top, Nominally 0 V Reference Voltage Sense Top Reference Voltage Middle, Nominally -1 V Reference Voltage Force Bottom, Nominally -2 V Reference Voltage Sense Bottom Analog Input Voltage, Can Be Either Voltage or Sense Digital Ground Data Output Bank A Data Output Bank B Data Ready Bank A Not Data Ready Bank A Data Ready Bank B Not Data Ready Bank B Overrange Output Bank A Overrange Output Bank B Clock Input Clock Input
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
D2B D3B D4B VEE VEE D5B DGND D6B DGND D7B DGND D8B N/C N/C AGND AGND AGND AGND VEE VEE VRBF VEE VEE VRBS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VRTF VRTS VRM VRBF VRBS VIN DGND D0-D7A D0-D7B DRA
DRA
MQUAD
DRB
DRB
D8A D8B CLK
CLK
ORDERING INFORMATION
PART NUMBER SPT7750AIK SPT7750BIK SPT7750BCU DESCRIPTION ILE = 1.0 LSB ILE = 1.5 LSB ILE = 1.5 LSB TEMPERATURE RANGE -25 to +85 C -25 to +85 C +25 C PACKAGE 80L MQUAD 80L MQUAD Die*
*Please see the die specification for guaranteed electrical performance.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
www.fairchildsemi.com
AGND AGND VEE VEE AGND AGND N/C VIN VIN N/C VRM AGND AGND VEE VEE VEE
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
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